NROM semiconductor memory devices (NROM=Nitride Read Only Memory) use inherent physical properties of the oxide-nitride-oxide (ONO) gate dielectric and known programming, reading and erasing mechanisms to provide memory cells having two bits per cell. The storage density in NROM semiconductor memory devices is thus twice as high as in conventional EEPROM semiconductor memory devices.
FIG. 4 shows a known NROM semiconductor memory device.
In FIG. 4, reference symbol 1 denotes a p−-type semiconductor substrate, reference symbol S denotes an n+-type source region, reference symbol D denotes an n+-type drain region, reference symbol FO denotes field oxide regions, reference symbol DD denotes an ONO triple dielectric, reference symbol WL denotes a word line as a gate connection, reference symbols B1 and B2 respectively denote a first and a second bit, and reference symbol LC denotes local charge accumulation regions corresponding to the bits B1 and B2.
An NROM semiconductor memory device of this type is described, for example, in B. Eitan, IEEE Electronic Device Letters 21, pages 543 ff, 2000.
The memory cell shown is an n-channel MOSFET in which the gate dielectric is an ONO triple dielectric DD. In order to form the bits B1 and B2, narrowly distributed charge accumulations in the two charge accumulation regions LC in the nitride may be programmed, read and erased. In this case, the localized charge distributions are produced such that they are themselves aligned with the edges of the channel. The NROM memory cell is programmed by injecting hot electrons. Typical programming voltages are VDS=5 V between the drain and the source and VG=9 V at the gate.
A method for fabricating an NROM semiconductor memory device of this type is disclosed, for example, in EP 1 073 120 A2.
The fact that a punch-through between the drain D and the source S of the respective MOSFET can occur when there are excessively high voltages at the drain, in particular if the transistor has a short channel length of typically less than 250 nm, has proved to be disadvantageous in these known NROM memory cells.
FIG. 5 shows another known an NROM semiconductor memory device.
This NROM semiconductor memory device is described in the earlier German application DE 102 04 873.8. In contrast to the NROM semiconductor memory device shown in FIG. 4, the MOSFETs are u-shaped in this case, thus allowing the undesirable tendency to a punch-through to be reduced since the channel length is longer than in the planar transistor for the same amount of area taken up.
In particular, in FIG. 5, T1″, T2″, T3″ denote a first, second and third u-shaped MOSFET. I denotes TEOS isolation regions, and G denotes a polysilicon gate which is connected to a word line WL made of tungsten.
However, initial measurements on NROM semiconductor memory devices of this type have revealed that, in this case, the problem of a punch-through from one transistor to an adjacent transistor can arise, as indicated in FIG. 5 by the arrow PT between the transistors T1″ and T2″. This punch-through occurs, in particular, when the distance between the adjacent transistors becomes smaller and smaller. The punch-through stems from the fact that the two transistors are at the same potential on account of the common word line. In addition, a punch-through between the channels may occur, thus reducing the production of channel hot electrons.